Semicon 2.0 Notified: India's ₹1,27,500-Crore Semiconductor Mission Phase 2 — Indigenous Chip Design, 3-nm Roadmap, and Semiconductor Sovereignty

Why in News

On August 31, 2026, the Ministry of Electronics and Information Technology (MeitY) formally notified Semicon India Programme 2.0 (Semicon 2.0) — the second phase of India's flagship semiconductor mission. The Union Cabinet had approved the programme on July 15, 2026, with a total financial outlay of ₹1,27,500 crore over the plan period. The notification details eligibility criteria, incentive structures, and a roadmap across six pillars and ten categories — expanding India's ambition from chip assembly to full-stack semiconductor sovereignty.

Background

Semiconductors are the foundational component of the modern digital economy: every smartphone, electric vehicle, satellite, defence system, and medical device depends on chips. The global semiconductor market stood at approximately $650 billion in 2025 and is projected to exceed $1 trillion by 2030. India imports semiconductors worth approximately $25 billion per year, making supply-chain self-reliance a matter of both economic and national security.

India possesses one of the world's strongest semiconductor design talent bases — approximately 20% of global VLSI (Very Large Scale Integration) design engineers are Indian, and over 3,000 companies work in chip design. Yet until recently, India had no domestic semiconductor fabrication facility.

Phase 1 — Semicon India Programme (December 2021)

The original Semicon India Programme was approved in December 2021 with an outlay of ₹76,000 crore, focused on three segments:

• Silicon semiconductor fabs (approved: Tata Electronics-PSMC fab in Dholera, Gujarat)
• Display fabs
• Compound semiconductors, silicon photonics, OSAT/ATMP (approved: Micron Technology assembly and testing plant in Sanand, Gujarat; CG Power, Kaynes Semicon, HCL-Foxconn)

Phase 1 focused primarily on attracting investments and setting up back-end assembly, testing, marking and packaging (ATMP) and outsourced semiconductor assembly and testing (OSAT) capacity — the less capital-intensive end of the semiconductor value chain. Phase 2 addresses the entire chain, including front-end fabrication at advanced nodes and the creation of indigenous intellectual property.

Timeline

Current Developments

The August 31, 2026 notification from MeitY spells out the full operational framework of Semicon 2.0:

• Financial outlay: ₹1,27,500 crore (significantly larger than Phase 1's ₹76,000 crore).
• Fiscal support: 40% government fiscal support for silicon wafer fabs, structured across capital expenditure incentives.
• Six pillars: (1) Semiconductor Fabs (silicon, compound, photonics), (2) Chip Design and IP, (3) Equipment and Materials, (4) Advanced Packaging, (5) Research and Development, and (6) Talent and Skill Development.
• Ten categories: Detailed eligibility under each pillar, now including startups, MSMEs, and research institutions — a departure from Phase 1's focus on large corporates.
• R&D allocation: ₹1,000 crore earmarked for industry-led research and training centres for FY 2026-27.
• Advanced nodes roadmap: A clearly defined pathway to 3-nanometre and 2-nanometre process technology by 2035.

Key Facts

• Programme name: Semicon India Programme 2.0 (Semicon 2.0) / India Semiconductor Mission 2.0 (ISM 2.0)
• Administering ministry: Ministry of Electronics and Information Technology (MeitY)
• Implementing agency: India Semiconductor Mission (ISM), set up under MeitY as a specialist unit
• Total outlay: ₹1,27,500 crore (approx. $15.3 billion at current rates)
• Cabinet approval date: July 15, 2026
• Notification date: August 31, 2026
• Global semiconductor market size (2025): ~$650 billion
• India's annual chip import bill: ~$25 billion
• India's share of global chip design engineers: ~20%
• Domestic demand coverage target by 2029: 70–75%
• Advanced node target by 2035: 3-nm and 2-nm
• A nanometre (nm): One billionth of a metre; smaller nodes = more transistors per chip = higher performance and efficiency

Constitutional Provisions

Semiconductor policy derives its constitutional basis from multiple provisions:

• Schedule VII, List I (Union List), Entry 52: Industries whose control by the Union is declared by Parliament to be expedient in the public interest — the basis for central regulation of the semiconductor industry under the IDR Act.
• Article 51A(h) — Fundamental Duty: Every citizen shall develop the scientific temper, humanism, and the spirit of inquiry and reform — invoked by the government to build a domestic innovation culture in semiconductors.
• Article 246: Parliament's exclusive power to legislate on Union List subjects, including strategic industries.
• Article 282: Enables the Union to make grants for public purposes — the legal basis for fiscal incentives and PLI (Production Linked Incentive) disbursements.

Legal Framework

• Industries (Development and Regulation) Act, 1951 (IDR Act): Governs the semiconductor industry as a scheduled industry.
• Information Technology Act, 2000: Provides the broader digital infrastructure legal framework within which semiconductor policy operates.
• Modified Special Incentive Package Scheme (M-SIPS): The predecessor fiscal incentive scheme for electronics manufacturing (now subsumed into ISM framework).
• National Electronics Policy 2019: Set the vision of a $400 billion electronics manufacturing sector and $100 billion exports by 2025 — Semicon 2.0 builds on this foundation.
• Design Linked Incentive (DLI) Scheme: Part of Phase 1, continued and expanded under Phase 2 to nurture chip design startups.

Institutional Framework

• India Semiconductor Mission (ISM): A specialist, autonomous body under MeitY, serves as the nodal agency for implementation, approvals, monitoring, and coordination.
• Cabinet Committee on Economic Affairs (CCEA): Approved Phase 1 and Phase 2 investments.
• MeitY: The nodal ministry for policy design, notification, and oversight.
• Invest India: Facilitates foreign direct investment into semiconductor projects.
• VLSI Society of India (VSI): Industry body for chip design ecosystem.
• International partnerships: Semiconductor cooperation under India-US ICET (Initiative on Critical and Emerging Technologies), Quad Semiconductor Supply Chain Initiative, and bilateral agreements with Japan, the EU, and Taiwan.

Economic Dimensions

Semiconductors are classified among the most strategically valuable commodities of the 21st century — often called "the new oil." India's chip import dependency (~$25 billion per year) is a structural current account vulnerability. Phase 2's ₹1,27,500 crore outlay is projected to catalyse a multiplier effect: every rupee invested in semiconductor manufacturing generates an estimated 5–7 rupees in broader economic activity across electronics, defence, automotive, telecom, and healthcare.

Employment: Phase 1 alone is expected to create over 1 lakh direct jobs; Phase 2 — by including MSMEs, startups, and training institutions — is expected to scale this manifold and create 5–7 lakh direct and indirect jobs in the semiconductor and electronics ecosystem by 2030.

Banking and financial angle: The ISM operates through fiscal incentives (40% government share in project costs) rather than direct lending. However, domestic banks — particularly SBI and PNB — are co-financing Phase 1 fab projects. The ₹1,27,500-crore outlay is a multi-year commitment that will support India's capital expenditure (capex) cycle and sustain investor confidence in high-tech manufacturing.

Export potential: India's chip design sector already exports over $60 billion worth of design services annually. Domestic fabrication capacity would allow India to capture the higher-margin value of manufacturing in addition to design — fundamentally altering the trade balance in electronics.

Environmental Dimensions

Semiconductor fabrication is among the most resource-intensive industrial processes. A single wafer fab can consume millions of litres of ultrapure water per day and significant quantities of specialty chemicals. Semicon 2.0 mandates green manufacturing standards for approved fabs, including:

• Water recycling and zero-liquid-discharge requirements
• Hazardous chemical waste management protocols
• Energy efficiency norms aligned with the Bureau of Energy Efficiency's (BEE) standards
• Alignment with SDG 9 (Industry, Innovation, Infrastructure) and SDG 13 (Climate Action)

India's decision to site fabs in areas like Dholera (Gujarat) — a Special Investment Region with planned infrastructure — minimises environmental disruption compared to ad-hoc industrial siting.

Social Dimensions

The inclusion of MSMEs, startups, and training institutions in Phase 2 marks a deliberate shift toward broader social participation in the semiconductor economy:

• Talent pipeline: ₹1,000 crore earmarked for industry-led training centres in FY 2026-27; IITs, NITs, and IIITs to be part of chip-design skilling curricula.
• Women in STEM: ISM has committed to gender-inclusive hiring norms for funded facilities.
• Regional spread: Approved facilities span Gujarat (Dholera, Sanand), Assam (chip design hub), and Uttar Pradesh — supporting lagging-region industrialisation.
• Tribal and SC/ST entrepreneurs: The MSME window under Phase 2 includes preferential scoring for firms with SC/ST promoters.

International Relations

India's semiconductor ambition is inseparable from the global geopolitical context:

• China+1 strategy: Global companies are actively diversifying semiconductor supply chains away from China and Taiwan, making India's timing strategically optimal.
• India-US ICET: Semiconductor co-production and technology transfer agreements, including US CHIPS Act-aligned partnerships.
• Quad Semiconductor Supply Chain Initiative: India, US, Japan, and Australia are building a resilient, trusted semiconductor supply chain.
• India-Japan partnership: Japanese companies (Renesas, Kioxia) are in discussions for design and packaging collaborations.
• India-Taiwan: PSMC (a Taiwanese foundry) is co-investing in the Tata fab in Dholera — a landmark technology transfer arrangement.
• EU-India Trade and Technology Council (TTC): Semiconductors are a priority cooperation area.

Challenges

• Capital intensity: A cutting-edge semiconductor fab costs $10–20 billion to build; even assembly plants cost $1–2 billion, demanding sustained government and private investment.
• Equipment dependency: Advanced lithography machines (especially EUV — Extreme Ultraviolet — from ASML) are subject to Dutch and US export controls, limiting access to the most advanced nodes.
• Water stress: High water consumption of fabs is a challenge in water-stressed regions; zero-liquid-discharge compliance adds cost.
• Long gestation: A new fab takes 3–5 years to build and another 2–3 years to achieve full yield — returns are not immediate.
• Skilled workforce gap: While India has strong design talent, process engineering, fab operation, and materials science capabilities are nascent and need development.
• Ecosystem depth: Chemicals, specialty gases, precision equipment — India imports virtually all of these; building a domestic supply chain for them takes a decade.

Government Initiatives

• PLI Scheme for Large Scale Electronics Manufacturing (₹40,951 crore): Incentivises electronics production across the value chain.
• Electronics Manufacturing Clusters (EMC 2.0): Builds plug-and-play infrastructure for electronics firms.
• Design Linked Incentive (DLI) Scheme: Financial support for chip design startups — up to ₹15 crore per startup over 3 years.
• National Quantum Mission (2023): Complements the semiconductor mission by building quantum computing hardware competencies.
• National AI Mission: AI accelerator chips (GPUs) are a target segment for ISM 2.0.
• Semicon India Future Design portal: Facilitates co-design partnerships between Indian VLSI talent and global chipmakers.

Way Forward

The NITI Aayog's Technology Vision document identifies semiconductors as a critical enabler across all Industry 4.0 sectors. Key recommendations anchored to authoritative bodies include:

• Establish a National Semiconductor Research Institute (recommended by the Parliamentary Standing Committee on Science and Technology) to bridge the gap between academic research and industrial fab-ready processes.
• Accelerate the Chip Design IP monetisation ecosystem — India must move from service-based design to IP ownership; 2nd-generation ISM should ring-fence IP created by DLI-funded startups.
• Adopt a whole-of-government approach (Finance Commission principle of cooperative federalism): state governments to provide land, water, and single-window clearances while the Centre funds capital incentives.
• Build a critical minerals-to-chip supply chain: India's rare earth and critical mineral deposits (gallium, germanium, indium) can seed a domestic compound semiconductor materials industry — a priority identified in the Economic Survey 2025–26.
• Ensure green fab standards from the outset to avoid a phase-out crisis later — BEE and MeitY to issue joint Green Fab norms within 12 months of Semicon 2.0 notification.

Possible Mains Questions

1. "India's Semicon 2.0 is not merely an industrial policy but a strategic response to a geopolitically fractured global supply chain." Critically examine the statement, analysing the opportunities and structural challenges India faces in achieving semiconductor sovereignty. (GS-III, 250 words)
2. Discuss the role of the India Semiconductor Mission in advancing India's 'Atmanirbhar Bharat' objectives. How does Phase 2 differ from Phase 1 in scope and ambition, and what institutional reforms are necessary to sustain this momentum? (GS-III, 150 words)

Possible Prelims MCQs

1. Q: With reference to Semicon India Programme 2.0 (Semicon 2.0), notified in August 2026, which of the following statements is/are correct?
   (1) Its total financial outlay is ₹1,27,500 crore.
   (2) It provides 40% fiscal support specifically for silicon wafer fabs.
   (3) It is implemented by the Ministry of Heavy Industries.
   A: 1 and 2 only | Explanation: Semicon 2.0 is implemented by MeitY through India Semiconductor Mission, not the Ministry of Heavy Industries. Statements 1 and 2 are correct.
2. Q: The term 'nanometre (nm)' in the context of semiconductor manufacturing refers to:
   (a) The physical size of a semiconductor chip in millimetres
   (b) The power consumption rating of a semiconductor device
   (c) The size of the smallest features (transistors/gates) in a chip manufacturing process
   (d) The operating voltage of the chip
   Answer: (c) | Explanation: In semiconductor parlance, a node/process node measured in nm refers to the minimum feature size (transistor gate length or equivalent) — smaller nm = more transistors, higher performance, lower power.

Essay Dimensions

1. Semiconductors: The silicon foundation of India's digital sovereignty
2. From design to fabrication: India's long journey up the chip value chain
3. Geopolitics and global supply chains: India's semiconductor opportunity in a fractured world
4. Technology, talent, and trade: The triple imperative of India's semiconductor mission
5. Can India become a chip-making nation? Lessons from South Korea, Taiwan, and the United States

Interview Questions

1. How does India's Semicon 2.0 differ from the US CHIPS Act or the EU Chips Act in design philosophy and scale?
2. India has 20% of global VLSI design talent but negligible fab capacity. Why has this translation not happened earlier, and what has changed?
3. What is a 'fabless' semiconductor company? Give Indian examples and explain how Semicon 2.0 supports them differently from Phase 1.
4. What is EUV lithography, and why is access to ASML's machines a geopolitical issue for India's advanced node ambitions?
5. How does the India-Taiwan PSMC arrangement differ from a simple technology licence, and why does it matter for semiconductor self-reliance?

FAQ

Q: What is the difference between Semicon India Programme Phase 1 and Semicon 2.0?

Phase 1 (₹76,000 crore, approved 2021) focused mainly on attracting foreign investment in chip assembly, testing, and back-end packaging (ATMP/OSAT) and one front-end fab (Tata-PSMC). Semicon 2.0 (₹1,27,500 crore, notified August 2026) covers the full chip value chain — from raw materials and equipment to indigenous chip design IP, R&D, advanced packaging, and talent, and now includes startups, MSMEs, and research institutions.

Q: What is the India Semiconductor Mission (ISM)?

ISM is a specialist autonomous body set up under MeitY to serve as the nodal implementation agency for India's semiconductor policies — handling project approvals, incentive disbursement, ecosystem development, and international partnerships.

Q: Why are advanced semiconductor nodes (3 nm, 2 nm) important?

Smaller nodes allow more transistors per chip, delivering greater processing power at lower energy consumption — essential for AI accelerators, 5G/6G chips, defence electronics, and next-generation consumer devices. Currently only TSMC (Taiwan) and Samsung (South Korea) produce 3-nm chips at scale; ASML's EUV lithography machines are needed for sub-7 nm nodes.

Q: Which state hosts the first approved semiconductor fab under ISM?

Gujarat. The Tata Electronics-PSMC (Taiwan) fab is being built in the Dholera Special Investment Region; Micron Technology's assembly and testing plant is in Sanand, Gujarat.

Further Reading

• PIB: India Semiconductor Mission 2.0 — pib.gov.in
• India Semiconductor Mission official portal — ism.gov.in
• MeitY — National Electronics Policy 2019